1. Field of the Invention
The present invention relates to a field effect type semiconductor device, and more particularly to a field effect type semiconductor device suitable for use with a field effect type device such as, for example, an HEMT (High Electron Mobility Transistor), an MESFET (Metal Semiconductor Field Effect Transistor) and so forth formed from compound semiconductor such as an InP material.
2. Description of the Related Art
In recent years, an HEMT is applied to signal processing circuits of optical communication systems, high speed digital circuits and so forth because it has a superior high-speed characteristic. Since the HEMT particularly has a superior low-noise characteristic, it is expected to be applied also to an amplifier for a microwave or millimeter wave band.
Meanwhile, in order to allow a digital circuit to operate at a high speed, it is demanded to raise the value of transconductance (gm) which is a device parameter relating to an amplification coefficient of a device and the value of a cutoff frequency (fT) of a current gain which is an upper limit to the frequency of amplification operation regarding a current gain of a transistor.
For example, as a transistor capable of operating at a high speed, an HEMT (InP-HEMT) formed using an InP related material can be listed. However, if the circuit scale increases, then reduction of the chip area and suppression of power consumption are required.
Generally, the HEMT operates in a depletion mode (D-mode). Therefore, electric current continues to flow also in a standby state, and it is difficult to achieve low power consumption operation.
Therefore, in order to allow an HEMT to operate at a high speed with lower consumption power, it is necessary to implement an InP-HEMT which can operate in an enhancement mode (E-mode) or an InP-HEMT of the E-mode/D-mode complementary type.
For example, Japanese Patent Laid-Open No. 10-209434 discloses a transistor wherein the E-mode and the D-mode are formed separately from each other depending upon whether or not an etching stopper layer is formed just under the gate electrode. The etching stopper layer is formed from InP.
Published Japanese Translation of a PCT Application, No. 2004-511913 discloses an HEMT wherein the E-mode and the D-mode are fabricated separately from each other depending upon whether or not a barrier layer (etching stop layer) is formed under the gate electrode. The barrier layer is formed from InGaP.
Japanese Patent Laid-Open No. 2003-23016 discloses a transistor device wherein the E-mode and the D-mode are fabricated separately from each other by forming two etching stop layers. Both of the etching stop layers are formed from InGaP.